Representing the culmination of more than 200 man-years of collective development by some of the most experienced software and hardware technologists in the semiconductor industry, SEAforth® multicore processors offer unprecedented flexibility and scalability.  Derived from a proprietary Scalable Embedded Array™ (SEA) Platform, SEAforth solutions are poised to raise the performance-per-watt bar in a host embedded applications.

A single-chip SEAforth solution combines A/D and D/A converters with an array of processor cores, each operating at 700 million instructions per second while collectively dissipating only 150mW in a typical application.  Powerful I/O makes each SEAforth solution a true system-on-chip that can be used individually or interconnected with multiple SEAforth chips to create an expansive SEA of processors to handle numerous tasks.

Application code written in compact VentureForth™ is stored in external Flash memory.  At boot, the code is read through one of the SPI ports and ripple-loaded into the RAM of each core, with the appropriate code going to the matching core.  ROM contains the core's BIOS, with each core containing a set of BIOS routines appropriate to it.  Forthlet™ code objects that can be stored on one core and executed on another contain routing routines for moving data from core to core around the chip, math routines, and in the case of edge cores, code that sets up the I/O pins connected to those cores.

Key to blazing speed of the SEAforth family is the use of asynchronous circuit design throughout the chip.  There is no central clock with billions of dumb nodes dissipating useless power.  All SEAforth cores communicate with each other in a fully asynchronous fashion that does not rely on status bits or handshake lines.  Significantly, the processor cores are internally asynchronous themselves.

While each core has its own ring oscillator running at a nominal 700MHz, it provides only the most basic timing signals within the core.  Accordingly, each core runs as fast as the native speed of the silicon will allow.  There are no clocks throttling down the execution speed to some artificial level.  Where it is necessary to match the speed of the array to real-time speeds such as video framing, a crystal can be driven by any I/O pins of a given core, which can then be used to pass time messages to other cores as appropriate. 



© 2010 IntellaSys, A TPL Group Enterprise.